1. Field of the Invention
The present invention generally relates to superconducting circuits utilizing a single flux quantum, and particularly relates to a superconducting circuit that generates a high-frequency clock through frequency multiplication.
2. Description of the Related Art
As a macroscopic quantum effect of superconductor, a loop formed by superconductor results in magnetic flux being quantized within the loop. The minimum unit of magnetic flux that is quantized in superconductor is called an SFQ (single flux quantum). An SFQ circuit is a logic circuit that operates with magnetic flux quantum serving as information carriers. Logic “1” is represented by a state in which an SFQ is present in a superconducting loop including two Josephson junctions, and logic “0” is represented by a state in which an SFQ is absent.
A number of superconducting loops, each of which is the basic structure of the SFQ circuit, are connected together to form a ladder-type line comprised of superconductors and Josephson junctions. This is called a JTL (Josephson transmission line), and allows magnetic flux quantum to propagate. An SFQ generated in a given loop causes the switching of a next Josephson device, resulting in an SFQ being generated in the next loop. This chain reaction allows an SFQ to propagate. In this manner, various logic circuits such as flip flops or the like can be formed by use of the SFQ circuit. It is expected that such SFQ circuit is applicable to various analog/digital processing circuits, including circuits having analog circuit elements, such as A/D converters for use for high-speed signals or small-level signals and superconducting samplers for detecting high-speed signals.
These superconducting analog/digital circuits need a clock signal having high frequency with high precision. In order to provide a sigma-delta A/D converter of a superconductor/semiconductor-hybrid type capable of processing 14-bit data with a frequency band of 10 MHz, for example, a sampling clock signal having a frequency of 20 GHz with a jitter smaller than 2 ps is required.
It is difficult, however, to supply a high-frequency signal from a semiconductor circuit operating in a room temperature environment to a superconducting circuit operating in a low temperature environment. This is because the signal line is required to have a long length and a narrow width in order to suppress heat propagation through the signal line, and it is difficult for the high-frequency signal to propagate through such a signal line.
Accordingly, it is preferable to supply a low frequency signal from the external to the superconducting circuit and to step up the frequency inside the superconducting circuit, rather than supplying a high-frequency signal directly from the external to the superconducting circuit. For example, a 10-GHz sinusoidal wave signal may be supplied from the external, and a doubler circuit may be provided inside the superconducting circuit chip to generate a 20-GHz clock pulse signal.
As a frequency-multiplier circuit implemented by use of a superconducting circuit, a ladder+conditioner circuit (Non-Patent Document 1) and a frequency multiplier (Non-Patent Document 2) are known. The ladder+conditioner circuit has a configuration in which a ladder circuit having a multiple stages of JTL circuits is combined with a JTL-based conditioner circuit. A pulse signal supplied as an input is delayed by the JTL circuit provided at each stage of the ladder circuit, and the plurality of pulse signals having respective delays are superimposed one over another. Then, the conditioner circuit performs an adjustment such that the intervals of the pulses of the superimposed pulse signals become equal to each other. It is difficult, however, to provide a delay with high precision for the JTL at each stage of the ladder circuit, and, also, there is a limit to the capability of the conditioner circuit to adjust the pulse intervals. It is thus difficult to set the pulse intervals to equal length with high precision.
The frequency multiplier is a circuit that steps up frequency based on a phase change brought about by utilizing a transformer coupling. FIG. 1 is a drawing showing an example of the circuit configuration of a related-art frequency multiplier.
A frequency multiplier 10 shown in FIG. 1 includes a transformer circuit 11, inductors 12-1 through 12-5, inductors 13-1 through 13-5, current sources 14-1 through 14-4, current sources 15-1 through 15-4, Josephson junctions 16-1 through 16-6, Josephson junctions 17-1 through 17-6, an inductor 18, a current source 19, and a Josephson junction 20. The primary-side inductor L11, of the transformer circuit 11 receives a sinusoidal electric current Iin from an alternating-current power supply 21 through a resistor 22.
In response, the secondary-side inductor L21 of the transformer circuit 11 generates a sinusoidal electric current IL, which initially runs in the direction shown by an arrow illustrated in FIG. 1. When the sum of the bias current supplied from the current source 14-1 to the Josephson junction 16-1 and the sinusoidal electric current IL exceeds a critical current, the Josephson junction 16-1 is switched on to generate an SFQ pulse. This pulse causes the Josephson junction 16-2 at the next stage to be switched on to generate an SFQ pulse. In this manner, pulses successively propagate to next stages.
When the phase of the sinusoidal electric current Iin supplied from the alternating-current power supply 21 advances to π, the sinusoidal electric current IL generated by the secondary-side inductor L21 of the transformer circuit 11 flows in the direction opposite the direction of the illustrated arrow. When the sum of the bias current supplied from the current source 15-1 to the Josephson junction 17-1 and the sinusoidal electric current IL exceeds a critical current, the Josephson junction 17-1 is switched on to generate an SFQ pulse. This pulse causes the Josephson junction 17-2 at the next stage to be switched on to generate an SFQ pulse. In this manner, pulses successively propagate to next stages.
The pulses propagating through the upper circuit of the frequency multiplier 10 and the pulses propagating through the lower circuit of the frequency multiplier 10 merge at a confluence buffer circuit 23. The Josephson junction 20 is switched by the merged signal, and the voltage generated by this switching is supplied as an output voltage VOUT.
In the above description, for the sake of convenience of explanation, switching is explained to occur in response to the sum of the bias current and the sinusoidal electric current IL exceeding the critical current of the Josephson junction. In reality, however, a magnetic flux quantum is generated due to the switching of the Josephson junction, such that a circulating current is generated and superimposed on the sinusoidal electric current IL. Because of this, the actual operation of the frequency multiplier 10 is slightly different from the above description. As a result, a problem occurs in that the pulse intervals are not set to equal intervals.
FIG. 2 is a drawing showing waveforms relating to the operation of the frequency multiplier 10 shown in FIG. 1. The letter designation (a) in FIG. 2 shows the alternating current Iin supplied to the primary-side inductor L11 of the transformer circuit 11. The letter designation (b) shows the current IL flowing through the secondary-side inductor L21 of the transformer circuit 11. The waveform illustrated by the dotted line in (b) is the sinusoidal electric current generated by the secondary-side inductor L21. The waveform illustrated by the solid line in (b) is the sum of the sinusoidal electric current shown by the dotted line and an electric current IΦ0 generated by the magnetic flux quantum generated by the switching of the Josephson junction. Accordingly, the current IL flowing through the secondary-side inductor L21 of the transformer circuit 11 has the waveform as shown by the solid line.
In the frequency multiplier 10 shown in FIG. 1, the upper circuit and lower circuit connected to the respective ends of the secondary-side inductor L21 of the transformer circuit 11 need to have symmetrical structures in order to generate pulses at equal intervals. As shown in FIG. 2-(b), therefore, a threshold current (critical current) Ith(J1) of the Josephson junction 16-1 and a threshold current Ith(J2) of the Josephson junction 17-1 have the same magnitude (with opposite signs reflecting their opposite current directions).
As shown in FIG. 2-(b), the initial state (the state in which no magnetic flux quantum is present) lasts until time t1, and, in this state, the current IL flowing through the secondary-side inductor L21 is equal to the sinusoidal electric current illustrated by the dotted line. At the time t1, the current IL exceeds the threshold current Ith(J1) (which is the threshold current for the current IL, and includes the contribution from the bias current supplied from the current source 14-1). In response, the Josephson junction 16-1 is switched on such that a magnetic flux quantum is generated in the superconducting closed loop including the inductor L21, thereby generating a circulating current IΦ0 flowing counterclockwise in the loop. The current IL running through the secondary-side inductor L21 is thus deviated from the sinusoidal electric current by the amount equal to the circulating current IΦ0. Also, the pulse generated by the switching of the Josephson junction 16-1 propagates through the circuit, so that the voltage V1 shown in the upper circuit of FIG. 1 exhibits a pulse-like change (i.e., an SFQ pulse) as shown in FIG. 2-(c).
Thereafter, at the time t2, the current IL exceeds the threshold current Ith(J2) (which is the threshold current for the current IL, and includes the contribution from the bias current supplied from the current source 15-1). In response, the Josephson junction 17-1 is switched on such that a magnetic flux quantum is generated in the superconducting closed loop including the inductor L21, thereby generating a circulating current IΦ0 flowing clockwise in the loop. The current IL flowing through the secondary-side inductor L21 is thus shifted by the amount equal to the circulating current IΦ0 so as to return to the magnitude equal to the sinusoidal electric current. The magnetic flux quantum generated at the time t1 and the magnetic flux quantum generated at the time t2 are canceled with each other, resulting in the state in which no magnetic flux quantum is present. Also, the pulse generated by the switching of the Josephson junction 17-1 propagates through the circuit, so that the voltage V2 shown in the lower circuit of FIG. 1 exhibits a pulse-like change as shown in FIG. 2-(d).
At time t3, the current IL exceeds the threshold current Ith(J2). In response, the Josephson junction 17-1 is switched on such that a magnetic flux quantum is generated in the superconducting closed loop including the inductor L21, thereby generating a circulating current IΦ0 flowing clockwise in the loop. The current IL flowing through the secondary-side inductor L21 is thus deviated from the sinusoidal electric current by the amount equal to the circulating current IΦ0. Because of the associated pulse propagation, the voltage V2 shown in FIG. 2-(d) exhibits a further pulse-like change.
At time t4, the current IL exceeds the threshold current Ith(J1). In response, the Josephson junction 16-1 is switched on such that a magnetic flux quantum is generated in the superconducting closed loop including the inductor L21, thereby generating a circulating current IΦ0 flowing counterclockwise in the loop. The current IL flowing through the secondary-side inductor L21 is thus shifted by the amount equal to the circulating current IΦ0 so as to return to the magnitude equal to the sinusoidal electric current. The magnetic flux quantum generated at the time t3 and the magnetic flux quantum generated at the time t4 are canceled with each other, resulting in the state in which no magnetic flux quantum is present. Because of the associated pulse propagation, the voltage V1 shown in FIG. 2-(c) exhibits a further pulse-like change.
In the manner as described above, four pulses are generated at timings t1, t2, t3, and t4 during one cycle T of the input sinusoidal wave. These pulses are merged at the confluence buffer circuit 23, so that the output voltage VOUT exhibits a waveform as shown in FIG. 2-(e). In this output voltage VOUT, the time intervals between the pulses are Δt1, Δt2, Δt1, Δt2, and so on.
The pulse at the time t1 and the pulse at the time t3 are generated at the timing dependent on the waveform of the sinusoidal electric current as shown in FIG. 2-(b), so that these pulses are distanced from each other by half a cycle of the sinusoidal wave. Accordingly, there is no problem with the precision of the timing of these pulses. Namely, Δt1+Δt2 is equal to half the cycle of the input sinusoidal wave in FIG. 2-(e).
The pulse at the time t2 and the pulse at the time t4 are generated at the timing dependent on the waveform made by superimposing the circulating current IΦ0 on the sinusoidal electric current as shown in FIG. 2-(b). Accordingly, the interval between the pulse at the time t1 and the pulse at the time t2 as well as the interval between the pulse at the time t3 and the pulse at the time t4 are independent of the input sinusoidal wave. Namely, Δt1 and Δt2 shown in FIG. 2-(e) are not individually a quarter of one cycle of the input sinusoidal wave, but are independent of the cycle of the input sinusoidal wave. Further, the magnitude of the circulating current IΦ0 fluctuates depending on the circuit parameters, so that it is difficult to set the timing of the t2 pulse and t4 pulse with sufficient precision.
In this manner, it is difficult for the related-art frequency multiplier to generate a signal having pulses at equal intervals.
[Non-Patent Document 1] A. Yoshida et al, “Frequency Multiply Circuit for Superconducting A/D Converter,” IEEE Transactions on Applied Superconductivity, Vol. 15, No. 2, pp 431-434 (2005)
[Non-Patent Document 2] J. C. Lin et al, “Design of SFQ-Counting Analog-to-Digital Converter,” IEEE Transactions on Applied Superconductivity, Vol. 5, No. 2, pp 2252-2259 (1995)
Accordingly, there is a need for a superconducting-circuit-based clock generating circuit that can generate a clock signal with high precision and small jitter.